Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A low cost 100 MHz analog test bus
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Pseudorandom testing for mixed-signal circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intrinsic response extraction for the removal of the parasitic effects in analog test buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of mixed-signal systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Wafer-level defect screening for "big-D/small-A" mixed-signal SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodologyfor mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time.To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.