Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
IEEE P1149.4-Almost a Standard
Proceedings of the IEEE International Test Conference
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
Time Domain Multiplexed TAM: Implementation and Comparison
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Pseudorandom testing for mixed-signal circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of mixed-signal systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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We present a new approach for TAM optimization and testscheduling in the modular testing of mixed-signal SOCs. A testplanning approach for digital SOCs is extended to handle analogcores in a plug-and-play fashion. A test wrapper based on anADC/DAC pair and a digital configuration circuit is designed foranalog cores such that these cores can be accessed through digitalTAMs. In this way, there is no dependence on an analog testbus and expensive mixed-signal testers. Experimental results arepresented for several ITC'02 SOC test benchmarks to which threeanalog cores are added. The results show that the testing of analogcores can be interleaved with the testing of digital cores to reducethe overall testing time for a mixed-signal SOC.