Analog BIST Generator for ADC Testing
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
IEEE Transactions on Computers
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Pseudorandom testing for mixed-signal circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
AMGIE-A synthesis environment for CMOS analog integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal SOCs reduces test cost. ATWs enable analog test using digital test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three ITC驴02 benchmark SOCs that have been augmented with five representative analog cores.