Optimal ordering of analog integrated circuit tests to minimize test time
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
Journal of Electronic Testing: Theory and Applications
IEEE P1149.4-Almost a Standard
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Core - Clustering Based SOC Test Scheduling Optimization
ATS '02 Proceedings of the 11th Asian Test Symposium
Test Scheduling and Test Access Architecture Optimization for System-on-Chip
ATS '02 Proceedings of the 11th Asian Test Symposium
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Crosstalk Effect Removal for Analog Measurement in Analog Test Bus
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A STAND-ALONE INTEGRATED TEST CORE FOR TIME AND FREQUENCY DOMAIN MEASUREMENTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A low cost 100 MHz analog test bus
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
BIST for Phase-Locked Loops in Digital Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Time Domain Multiplexed TAM: Implementation and Comparison
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Pseudorandom testing for mixed-signal circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intrinsic response extraction for the removal of the parasitic effects in analog test buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of mixed-signal systems-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient test access mechanism optimization for system-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Analog circuit test based on a digital signature
Proceedings of the Conference on Design, Automation and Test in Europe
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Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.