Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Test scheduling for core-based systems
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
An integrated system-on-chip test framework
Proceedings of the conference on Design, automation and test in Europe
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Test scheduling for core-based systems using mixed-integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A new design-for-test technique for reducing SOC test time
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power constrained and defect-probability driven SoC test scheduling with test set partitioning
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
IEEE Transactions on Computers
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Journal of Electronic Testing: Theory and Applications
Power-aware SoC test planning for effective utilization of port-scalable testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test time minimization for hybrid BIST of core-based systems
Journal of Computer Science and Technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling Tests for 3D Stacked Chips under Power Constraints
Journal of Electronic Testing: Theory and Applications
Power-aware system-on-chip test scheduling using enhanced rectangle packing algorithm
Computers and Electrical Engineering
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We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.