System chip test: how will it impact your design?
Proceedings of the 37th Annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Test Bus Sizing for System-on-a-Chip
IEEE Transactions on Computers
The design and optimization of SOC test solutions
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of Electronic Testing: Theory and Applications
On Concurrent Test of Core-Based SOC Design
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Journal of Electronic Testing: Theory and Applications
On-Chip Clock Faults' Detector
Journal of Electronic Testing: Theory and Applications
On Test Scheduling for Core-Based SOCs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
On Using IEEE P1500 SECT for Test Plug-n-Play
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Journal of Electronic Testing: Theory and Applications
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Searching for Global Test Costs Optimization in Core-Based Systems
Journal of Electronic Testing: Theory and Applications
A New FPGA for DSP Applications Integrating BIST Capabilities
Journal of Electronic Testing: Theory and Applications
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Delay Fault Testing of Core-Based Systems-on-a-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
InTeRail: A Test Architecture for Core-Based SOCs
IEEE Transactions on Computers
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Integration, the VLSI Journal
Low-power multi-core ATPG to target concurrency
Integration, the VLSI Journal
The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
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Test access is a major problem for system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip I/Os, special access mechanisms are required to test them after system integration. Efficient test access architecture should reduce test cost and time-to-market by minimizing test application time.We address several issues related to the design of test access architectures. Even though these design problems are NP-complete, they can be solved exactly using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but representative systems are solved using a public-domain ILP software package.