Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introducing Core-Based System Design
IEEE Design & Test
Test Requirements for Embedded Core-Based Systems and IEEE P1500
Proceedings of the IEEE International Test Conference
Scan chain design for test time reduction in core-based ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Efficient Wrapper/TAM Co-Optimization for Large SOCs
Proceedings of the conference on Design, automation and test in Europe
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
IEEE Transactions on Computers
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing
ATS '04 Proceedings of the 13th Asian Test Symposium
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test planning for modular testing of hierarchical SOCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a framework and an efficient method to determine SOC test schedules. We increase the test TAM widths by the framework. Our method deals with the traditional scan chains and reconfigurable multiple scan chains. Experimental results for ITC'02 SOC TEST Benchmarks show that we obtain better test application time when compared to previously published algorithms. Test access mechanism (TAM) and test schedule for System-On-chip (SOC) are challenging problems. Test schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a core section method based on generalized 2-D rectangle packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic to change the width of the TAM executing the core test. Therefore, a core can utilize different TAM width to complete test.