The efficient TAM design for core-based SOCs testing
WSEAS Transactions on Circuits and Systems
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
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Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and technology-mapped layouts. We present three hierarchical test planning and TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. These techniques are based on the reuse of existing TAM architectures within megacores and the optimization of the top-level TAM under the constraints imposed by "TAM-ed" megacores that are delivered either with or without a wrapper. We present a new megacore wrapper-design technique for the latter case. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design-transfer models involving hard megacores between the core vendor and the system integrator for hierarchical SOCs. Experimental results are presented for four ITC'02 SOC test benchmarks that contain megacores.