Advanced Engineering Mathematics: Maple Computer Guide
Advanced Engineering Mathematics: Maple Computer Guide
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Testing the 500-MHz IBM S/390 Microprocessor
IEEE Design & Test
The Road Ahead: The significance of packaging
IEEE Design & Test
Enhanced reduced pin-count test for full-scan design
Proceedings of the IEEE International Test Conference 2001
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
ICCD '03 Proceedings of the 21st International Conference on Computer Design
IEEE Transactions on Computers
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Journal of Electronic Testing: Theory and Applications
Defect-Aware SOC Test Scheduling
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Achieving High Test Quality with Reduced Pin Count Testing
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY
ITC '04 Proceedings of the International Test Conference on International Test Conference
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wafer-level modular testing of core-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EDA in IBM: past, present, and future
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test planning for modular testing of hierarchical SOCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modular SOC testing with reduced wrapper count
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Wafer-level testing (wafer sort) is used in the semiconductor industry to reduce packaging and test cost. However, a large number of wafer-probe contacts lead to higher yield loss. Therefore, it is desirable that the number of chip pins contacted by tester channels during wafer sort be kept small to reduce the yield loss resulting from improper contacts. Since test time and the number of contacted chip pins are major practical constraints for wafer sort, not all scan-based digital tests can be applied to the die under test. We propose an optimization framework based on mathematical programming (integer linear programming, nonlinear programming, and geometric programming) and fast heuristic methods. This framework addresses test-access mechanism (TAM) optimization and test-length selection for wafer-level testing of core-based digital system-on-chips (SoCs). The objective here is to design a TAM architecture and determine test lengths for the embedded cores such that the overall SoC defect-screening probability at wafer sort is maximized. Defect probabilities for the embedded cores, obtained using statistical yield modeling, are incorporated in the optimization framework. Simulation results are presented for five of the ITC'02 SoC Test benchmarks.