Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits
Journal of Electronic Testing: Theory and Applications
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Proceedings of the 40th annual Design Automation Conference
Test data compression using dictionaries with selective entries and fixed-length indices
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Nanometer Design: What are the Requirements for Manufacturing Test?
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
The use of genetic algorithm to reduce power consumption during test application
ICES'10 Proceedings of the 9th international conference on Evolvable systems: from biology to hardware
SOC test planning using virtual test access architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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