Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Enhanced reduced pin-count test for full-scan design
Proceedings of the IEEE International Test Conference 2001
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
THE LEADING EDGE OF PRODUCTION WAFER PROBE TEST TECHNOLOGY
ITC '04 Proceedings of the International Test Conference on International Test Conference
The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500 (Frontiers in Electronic Testing)
Testing for Faults in Wiring Networks
IEEE Transactions on Computers
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3D Integration: Technology and Applications
3D Integration: Technology and Applications
IEEE Std 1500 Enables Modular SoC Testing
IEEE Design & Test
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Contactless testing: possibility or pipe-dream?
Proceedings of the Conference on Design, Automation and Test in Europe
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Journal of Electronic Testing: Theory and Applications
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Journal of Electronic Testing: Theory and Applications
High-throughput TSV testing and characterization for 3D integration using thermal mapping
Proceedings of the 50th Annual Design Automation Conference
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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To meet customer's product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone manufacturing steps; these tests should be both effective and cost-efficient. The semiconductor industry is preparing itself now for three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs), which, due to their many compelling benefits, are quickly gaining ground. Test solutions need to be ready for this new generation of 'super chips'. 3D-SICs are chips where all basic, as well as most advanced test technologies come together. In addition, they pose some truly new test challenges with respect to complexity and cost, due to their advanced manufacturing processes and physical access limitations. This presentation focuses on the available solutions and still open challenges for testing 3D-SICs. It discusses flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip Design-for-Test (DfT) infrastructure required for 3D-SICs.