Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Contactless testing: possibility or pipe-dream?
Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a new framework to detect structural defects and characterize the variability in the electrical resistance of through-silicon vias (TSVs) in 3D ICs. Our method offers a number of advantages that have been hard to achieve in the past. In particular, the proposed framework provides high throughput TSV testing at pre-bonding stage. A resistive liquid electrode is placed at the back side of the device to conduct electric current from TSVs. The current passing through TSVs leads to heat generation which can be captured by a remote, high-sensitivity thermal camera. The captured thermal signatures from the TSVs are then contrasted against reference thermal maps generated from known good die and/or electro-thermal simulations of models of good TSVs. A proposed automatic classification technique is capable of determining the status of TSVs based on their thermal signatures. We demonstrate the viability of the proposed technique using extensive simulation results on realistic TSV configurations.