Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reducing the leakage and timing variability of 2D ICs using 3D ICs
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
Layout effects in fine grain 3D integrated regular microprocessor blocks
Proceedings of the 48th Design Automation Conference
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
Journal of Electronic Testing: Theory and Applications
High-throughput TSV testing and characterization for 3D integration using thermal mapping
Proceedings of the 50th Annual Design Automation Conference
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Journal of Electronic Testing: Theory and Applications
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Three-dimensional integrated circuit technology with through-silicon vias offers many advantages, including improved form factor, increased circuit performance, robust heterogenous integration, and reduced costs. Wafer-to-wafer integration supports the highest possible density of through-silicon vias and highest throughput; however, in contrast to die-to-wafer integration, it does not benefit from the ability to bond only tested and diced good die. In wafer-to-wafer integration, wafers are entirely bonded together, which can unintentionally integrate a bad die from one wafer to a good die from another wafer reducing the yield. In this paper, we propose solutions that maximize the yield of wafer-to-wafer 3-D integration, assuming that the individual die can be tested on the wafers before bonding. We exploit some of the available flexibility in the integration process, and propose wafer assignment algorithms that maximize the number of good 3-D ICs. Our algorithms range from scalable, fast heuristics to optimal methods that exactly maximize the yield of wafer-to-wafer 3-D integration. Using realistic defect models and yield simulations, we demonstrate the effectiveness of our methods up to large numbers of wafer stacks. Our results demonstrate that it is possible to significantly improve the yield in comparison to yield-oblivious wafer assignment methods.