Clock rate versus IPC: the end of the road for conventional microarchitectures
Proceedings of the 27th annual international symposium on Computer architecture
SOI technology for the GHz era
IBM Journal of Research and Development
Beyond the conventional transistor
IBM Journal of Research and Development
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Strategies for improving the parametric yield and profits of 3D ICs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Low-power clock distribution in a multilayer core 3d microprocessor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
3-D stacked CMOS inverters using Pt/HfO2 on Si substrate for vertical integrated CMOS applications
Microelectronic Engineering
Why should we do 3D integration?
Proceedings of the 45th annual Design Automation Conference
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Microelectronic Engineering
High aspect ratio copper through-silicon-vias for 3D integration
Microelectronic Engineering
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High-performance, cost-effective heterogeneous 3D FPGA architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
From 3D circuit technologies and data structures to interconnect prediction
Proceedings of the 11th international workshop on System level interconnect prediction
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
Three-dimensional silicon integration
IBM Journal of Research and Development
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
IBM Journal of Research and Development
Wafer-level 3D integration technology
IBM Journal of Research and Development
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
Scalability of network-on-chip communication architecture for 3-D meshes
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Spectrum: a hybrid nanophotonic-electric on-chip network
Proceedings of the 46th Annual Design Automation Conference
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
An SDRAM-aware router for Networks-on-Chip
Proceedings of the 46th Annual Design Automation Conference
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Microelectronic Engineering
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
Proceedings of the Conference on Design, Automation and Test in Europe
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC
Proceedings of the Conference on Design, Automation and Test in Europe
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Applications driving 3D integration and corresponding manufacturing challenges
Proceedings of the 48th Design Automation Conference
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
A novel graceful degradable routing algorithm for 3D on-chip networks
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A novel 3D NoC architecture based on De Bruijn graph
Computers and Electrical Engineering
Improving coherence protocol reactiveness by trading bandwidth for latency
Proceedings of the 9th conference on Computing Frontiers
Software—Practice & Experience
Spatial and temporal thermal characterization of stacked multicore architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on embedded systems for interactive multimedia services (ES-IMS)
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Journal of Electronic Testing: Theory and Applications
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design
Journal of Electronic Testing: Theory and Applications
An asymmetric adaptive-precision energy-efficient 3DIC multiplier
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Effect of TSV fabrication technology on power distribution in 3D ICs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A study of tapered 3-D TSVs for power and thermal integrity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New heuristic algorithms for low-energy mapping and routing in 3D NoC
International Journal of Computer Applications in Technology
AFRA: a low cost high performance reliable routing for 3D mesh NoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On effective TSV repair for 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.