An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Thermally robust clocking schemes for 3D integrated circuits
Proceedings of the conference on Design, automation and test in Europe
Buffered clock tree synthesis for 3D ICs under thermal variations
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Low-power clock distribution in a multilayer core 3d microprocessor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Pre-bond testable low-power clock tree design for 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Proceedings of the 47th Design Automation Conference
An efficient phase detector connection structure for the skew synchronization system
Proceedings of the 47th Design Automation Conference
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
On the skew-bounded minimum-buffer routing tree problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TSV array utilization in low-power 3D clock network design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees
Proceedings of the International Conference on Computer-Aided Design
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Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with minimum skew and latency. While there are a few related works in literature, none of them considers the reliability of TSVs. Accordingly, the failure of any TSV in the clock tree yields a bad chip. The naive solution using double-TSV can alleviate the problem. But the significant area overhead renders it less practical for large designs. In this paper, we propose a novel TSV fault-tolerant unit (TFU) that can provide tolerance against TSV failures in a 3D clock network. It makes use of the existing 2D redundant trees designed for pre-bond testing, and thus has minimum area overhead. Compared to the double TSV technique, the 3D clock network constructed by our TFUs can achieve 61% area reduction with 3.9% yield rate improvement on an industrial case. To the best of the authors' knowledge, this is the first practical work in literature that considers the fault tolerance of a 3D clock network.