Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A faster approximation scheme for timing driven minimum cost layer assignment
Proceedings of the 2009 international symposium on Physical design
Slew-aware clock tree design for reliable subthreshold circuits
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A fast general slew constrained minimum cost buffering algorithm
Microelectronics Journal
A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
IEEE Transactions on Circuits and Systems II: Express Briefs
Pre-bond testable low-power clock tree design for 3D stacked ICs
Proceedings of the 2009 International Conference on Computer-Aided Design
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Shedding physical synthesis area bloat
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the 2014 on International symposium on physical design
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As a prevalent constraint, sharp slew rate is often required in circuit design, which causes a huge demand for buffering resources. This problem requires ultrafast buffering techniques to handle large volume of nets while also minimizing buffering cost. This problem is intensively studied in this paper. First, a highly efficient algorithm based on dynamic programming is proposed to optimally solve slew buffering with discrete buffer locations. Second, a new algorithm using the maximum matching technique is developed to handle the difficult cases in which no assumption is made on buffer input slew. Third, an adaptive buffer selection approach is proposed to efficiently handle slew buffering with continuous buffer locations. Fourth, buffer blockage avoidance is handled, which makes the algorithms ready for practical use. Experiments on industrial netlists demonstrate that our algorithms are very effective and highly efficient: we achieve about 90x speedup and save up to 20% buffer area over the commonly used van Ginneken style buffering. The new algorithms also significantly outperform previous works that indirectly address the slew buffering problem.