ISPD '99 Proceedings of the 1999 international symposium on Physical design
Closed form expressions for extending step delay and slew metrics to ramp inputs
Proceedings of the 2003 international symposium on Physical design
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat
Proceedings of the 2004 international symposium on Physical design
Convex Optimization
Fast and flexible buffer trees that navigate the physical layout environment
Proceedings of the 41st annual Design Automation Conference
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane
Proceedings of the 2006 international symposium on Physical design
Efficient obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2007 international symposium on Physical design
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
Proceedings of the 2009 International Conference on Computer-Aided Design
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 19th international symposium on Physical design
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles
Proceedings of the 48th Design Automation Conference
Buffer insertion with adaptive blockage avoidance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Porosity-aware buffered Steiner tree construction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
Proceedings of the 2014 on International symposium on physical design
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In this paper, we study an often overlooked but very important and practical problem of building Buffering-aware Over-the-Block rectilinear Steiner minimum tree (BOB-RSMT). In most previous works, the routing resources over the IP blocks were simply treated as routing blockages, resulting in significant waste of routing resources on higher metal layers not utilized by internal intra-block routing. On the other hand, routing over large IP blocks needs special attention as there is no way to insert buffers inside hard IP blocks, which can lead to unresolvable slew/timing violations. In this paper, we propose a novel BOB-RSMT algorithm which helps reclaim the "wasted" over-the-block routing resources while meeting user-specified slew constraints. Our algorithm incrementally and efficiently migrates initial tree structures with buffering-awareness to meet slew constraints while minimizing wire length. It can handle complex blocks including rectilinear shapes. Our experiments on various benchmarks demonstrate very promising results. By utilizing over-the-block routing resources intelligently, we can save the outside-block wire length as well as the total wire length significantly compared with the conventional obstacle-avoiding rectilinear Steiner minimum tree (OA-RSMT) algorithms. BOB-RSMT also reduces the repeater count/area needed to satisfy slew constraints, which is very important for modern design closure.