A new approach to the rectilinear Steiner tree problem
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing
Proceedings of the 2003 international workshop on System-level interconnect prediction
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Finding obstacle-avoiding shortest paths using implicit connection graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2007 international symposium on Physical design
Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree
Proceedings of the 2008 international symposium on Physical design
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction
Proceedings of the 2008 international symposium on Physical design
An efficient rectilinear Steiner tree algorithm with obstacles
CSECS'06 Proceedings of the 5th WSEAS International Conference on Circuits, Systems, Electronics, Control & Signal Processing
Obstacle-avoiding rectilinear Steiner tree construction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
High-performance obstacle-avoiding rectilinear steiner tree construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture
IMCAS'09 Proceedings of the 8th WSEAS international conference on Instrumentation, measurement, circuits and systems
An O(n log n) path-based obstacle-avoiding algorithm for rectilinear Steiner tree construction
Proceedings of the 46th Annual Design Automation Conference
WSEAS Transactions on Circuits and Systems
Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree
Proceedings of the 2009 International Conference on Computer-Aided Design
Obstacle-avoiding rectilinear Steiner tree construction based on Steiner point selection
Proceedings of the 2009 International Conference on Computer-Aided Design
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles
Proceedings of the 48th Design Automation Conference
Obstacle-avoiding rectilinear Steiner minimum tree construction: an optimal approach
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles
Proceedings of the 2014 on International symposium on physical design
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach
Integration, the VLSI Journal
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Routing is one of the important phases in VLSI/ULSI physical design. The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is an essential part of routing since macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in the routing phase. Efficient OARSMT algorithms can be employed in practical routers iteratively. Recently, IC routing and related researches have been extended from Manhattan architecture (λ2-geometry) to Y- / X-architecture (λ3- / λ4-geometry) to improve the chip performance. This paper presents an O(nlogn) heuristic, λ-OASMT, for obstacle-avoiding Steiner minimal tree construction in the λ-geometry plane. Based on obstacle-avoiding constrained Delaunay triangulation, a full connected tree is constructed and then embedded into λ-OASMT by a novel method called zonal combination. To the best of our knowledge, this is the first work addressing the λ-OASMT problem. Compared with two most recent works on OARSMT problem, λ-OASMT obtains up to 30Kx speedup with an even better quality solution. We have tested randomly generated cases with up to 1K terminals and 10K rectilinear obstacles within 3 seconds on a Sun V880 workstation (755MHz CPU and 4GB memory). The high efficiency and accuracy of λ-OASMT make it extremely practical and useful in the routing phase, as well as interconnect estimation in the process of floorplanning and placement.