HARTS: A Distributed Real-Time Architecture
Computer - Special issue on real-time systems
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
On the Characterization of Multi-Point Nets in Electronic Designs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
The Y-architecture: yet another on-chip interconnect solution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Preferred direction Steiner trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the λ-geometry plane
Proceedings of the 2006 international symposium on Physical design
X-architecture placement based on effective wire models
Proceedings of the 2007 international symposium on Physical design
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
A near linear time approximation scheme for Steiner tree among obstacles in the plane
Computational Geometry: Theory and Applications
Approximation of octilinear steiner trees constrained by hard and soft obstacles
SWAT'06 Proceedings of the 10th Scandinavian conference on Algorithm Theory
| Hi-index | 0.00 |
λ-geometry routing has recently received much attention due to the potential for reduced interconnect length in comparison to today's prevalent Manhattan routing. An accurate cost-benefit analysis of λ-geometry routing is impossible without good estimation of the wirelength reduction expected when switching from Manhattan to λ-geometry routing. However, in the literature, estimates of wirelength improvements achieved by λ-geometry routing are usually for randomly generated nets, and the effect of λ-geometry-driven placement on the overall wirelength improvement is not properly considered. In this paper, we improve existing estimates for the wirelength reduction of various λ-geometry interconnect architectures. First, we give more accurate estimations of the expected wirelength reduction given by λ-geometry routing on Manhattan placements. We take into account the effect of wirelength-driven Manhattan placement on pin locations for nets with k=2, 3 and 4 pins, and observe smaller expected reductions compared to previous estimates based on nets randomly located in the plane. Second, we estimate the wirelength improvement achieved by λ-geometry placement and routing versus Manhattan placement and routing. Our estimate is based on a simulated annealing placer, driven by λ-geometry metrics. Finally, we discuss and analyze the "virtuous cycle" effect: reduction of overall wirelength results in decreased routing area, which in turn leads to further wirelength reduction.