On some distance problems in fixed orientations
SIAM Journal on Computing
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
Planar clock routing for high performance chip and package co-design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The X architecture: not your father's diagonal wiring
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
UST/DME: a clock tree router for general skew constraints
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Estimation of wirelength reduction for λ-geometry vs. manhattan placement and routing
Proceedings of the 2003 international workshop on System-level interconnect prediction
The Steiner Minimal Tree Problem in the lambda-Geormetry Plane
ISAAC '96 Proceedings of the 7th International Symposium on Algorithms and Computation
An Exact Algorithm for the Uniformly-Oriented Steiner Tree Problem
ESA '02 Proceedings of the 10th Annual European Symposium on Algorithms
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Buffered Clock Tree for High Quality IC Design
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Proceedings of the 42nd annual Design Automation Conference
Highly scalable algorithms for rectilinear and octilinear Steiner trees
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Planar-DME: a single-layer zero-skew clock tree router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
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As technology advances into nanometer territory, clock network layout plays an increasingly important role in determining circuit quality indicated by timing, power consumption, cost, power supply noise and tolerance to process variation. To alleviate the challenges to the existing routing algorithms due to the continuous increase of the problem size and the high-performance requirement, X-architecture has been proposed and applied to routing in that it can reduce wirelength and via counts, and thus improves the performance and routability compared with the conventional Manhattan routing. In this paper, we investigate zero skew clock routing using X-architecture based on an improved greedy matching algorithm (GMZSTX). The fitted Elmore delay model is employed to improve the accuracy over the Elmore delay model. The interactions among distance, delay balance and load balance are analyzed. Based on this analysis, an effective and efficient greedy matching scheme is suggested to reduce wire snaking and to get a more balanced clock tree. The proposed algorithm is simple and fast for practical applications. Experimental results on benchmark circuits show that our algorithm (GMZSTX) achieves a reduction of 8.15% in total wirelength, 30.19% in delay and 55.31% in CPU time on average compared with zero skew clock routing in the Manhattan plane (BB+DME-2, which means using the top-down balanced bipartition (BB) method [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II-Analog & Digital Signal Process 39 (11) (1992) 799-814] to generate the tree topology and using the Deferred-Merge Embedding (DME) algorithm [T.H. Chao, Y.C. Hsu, J.M. Ho, et al., Zero skew routing with minimum wirelength, IEEE Trans. Circuits Syst. II-Analog & Digital Signal Process 39 (11) (1992) 799-814] to embed the internal nodes), and reduces delay and CPU time by 17.44% and 62.21% on average over the BB+DME-4 method (which is similar to BB+DME-2, but routing in X-architecture). Our SPICE simulation further verifies the correctness of the resulting clock tree.