On optimal ordering of signals in parallel wire bundles
Integration, the VLSI Journal
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
Timing-aware power-optimal ordering of signals
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interconnect power and delay optimization by dynamic programming in gridded design rules
Proceedings of the 19th international symposium on Physical design
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In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay model. Thus our model has all the advantages of the Elmore delay model. It has a closed form expression as simple as the Elmore delay model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the Elmore delay model. In fact, most previous algorithms and programs based on Elmore delay model can use our model without much change. Most importantly, FED is significantly more accurate thanthe Elmore delay model. The maximum error in delay estimation is at most 2% for our model, compared to 8.5% for the scaled Elmore delay model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than Elmore delay model when applied to wire sizing.