A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Balanced block spacing for VLSI layout
Discrete Applied Mathematics - Special issue: graphs in electrical engineering, discrete algorithms and complexity
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Introduction to Algorithms
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
An O(nlogn) time algorithm for optimal buffer insertion
Proceedings of the 40th annual Design Automation Conference
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Convex Optimization
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Efficient Data Structure for Maxplus Merge in Dynamic Programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissible interconnect widths and spaces to a small set of discrete values with some interdependencies, so that traditional interconnect sizing by continuous-variable optimization techniques becomes impossible. We present a dynamic programming (DP) algorithm for simultaneous sizing and spacing of all wires in interconnect bundles (or bus structures), yielding the optimal power-delay tradeoff curve. It sets the width and spacing of all interconnects simultaneously, thus finding the global optimum. The DP algorithm is generic and can handle a variety of power-delay objectives, such as total power or delay, or weighted sum of both, power-delay product, max delay and alike. The algorithm consistently yields more than 10% dynamic power and 5% delay reduction for interconnect channels in industrial microprocessor blocks designed in 32 nanometer process technology, when applied as a post-layout optimization step to redistribute wires within interconnect channels of fixed width, without changing the area of the original layout.