Optimal orientations of cells in slicing floorplan designs
Information and Control
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Algorithms for multilevel logic optimization
Algorithms for multilevel logic optimization
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimal latch mapping and retiming within a tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Technology mapping using fuzzy logic
DAC '94 Proceedings of the 31st annual Design Automation Conference
Explicit evaluation of short circuit power dissipation for CMOS logic structures
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Transistor reordering for power minimization under delay constraint
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A simple algorithm for fanout optimization using high-performance buffer libraries
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Layout driven re-synthesis for low power consumption LSIs
DAC '97 Proceedings of the 34th annual Design Automation Conference
An exact solution to simultaneous technology mapping and linear placement problem
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together
DAC '98 Proceedings of the 35th annual Design Automation Conference
An &agr;-approxmimate algorithm for delay-constraint technology mapping
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
An integrated algorithm for combined placement and libraryless technology mapping
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Low-power technology mapping for mixed-swing logic
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic Synthesis and Verification
Readings in hardware/software co-design
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
An efficient technology mapping algorithm targeting routing congestion under delay constraints
Proceedings of the 2005 international symposium on Physical design
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
Proceedings of the 43rd annual Design Automation Conference
Performance-driven technology mapping with MSG partition and selective gate duplication
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Interconnect power and delay optimization by dynamic programming in gridded design rules
Proceedings of the 19th international symposium on Physical design
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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