DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Structured design implementation: a strategy for implementing regular datapaths on FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Module compaction in FPGA-based regular datapaths
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Efficient tree pattern matching (extended abstract): an aid to code generation
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Code Generation for Expressions with Common Subexpressions
Journal of the ACM (JACM)
A Retargetable C Compiler: Design and Implementation
A Retargetable C Compiler: Design and Implementation
Multiprocessors from a Software Perspective
IEEE Micro
An Efficient Technique for Mapping RTL Structures onto FPGAs
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A methodology for fast FPGA floorplanning
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Fast compilation for pipelined reconfigurable fabrics
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Proceedings of the 38th annual Design Automation Conference
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Fast placement approaches for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction generation and regularity extraction for reconfigurable processors
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On Using Tabu Search for Design Automation of VLSI Systems
Journal of Heuristics
The Garp Architecture and C Compiler
Computer
Adaptive Multiuser Online Reconfigurable Engine
IEEE Design & Test
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Minimizing routing configuration cost in dynamically reconfigurable FPGAs
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
A Placement/Routing Approach for FPGA Accelerators
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A graph covering algorithm for a coarse grain reconfigurable system
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
CPR: A Configuration Profiling Tool
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fast Online Placement for Reconfigurable Computing
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A C to Hardware/Software Compiler
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Efficient Place and Route for Pipeline Reconfigurable Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
BEE2: A High-End Reconfigurable Computing System
IEEE Design & Test
Physical resource binding for a Coarse-Grain reconfigurable array using evolutionary algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graph-Based Procedural Abstraction
Proceedings of the International Symposium on Code Generation and Optimization
A partitioning methodology that optimises the area on reconfigurable real-time embedded systems
EURASIP Journal on Applied Signal Processing
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
An incremental temporal partitioning method for real-time reconfigurable systems
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Towards a holistic CAD platform for nanotechnologies
Microelectronics Journal
High-level modelling and exploration of coarse-grained re-configurable architectures
Proceedings of the conference on Design, automation and test in Europe
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Multilevel optimization for large-scale hierarchical FPGA placement
Journal of Computer Science and Technology
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-overhead interconnect architecture for virtual reconfigurable fabrics
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
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By tailoring a compiler tree-parsing tool for datapath module mapping, we produce good quality results for datapath synthesis in very fast run time. Rather than flattening the design to gates, we preserve the datapath structure; this allows exploitation of specialized datapath features in FPGAs, retains regularity, and also results in a smaller problem size. To further achive high mapping speed, we formulate the problem as tree covering and solve it efficiently with a linear-time dynamic programming algorithm. In a novel extension to the tree-covering algorithm, we perform module placement simultaneously with the mapping, still in linear time. Integrating placement has the potential to increase the quality of the result since we can optimize total delay including routing delays.To our knowledge this is the first effort to leverage a grammar-based tree covering tool for datapath module mapping. Further, it is the first work to integrate simultaneous placement with module mapping in a way that preserves linear time complexity.