A methodology for fast FPGA floorplanning

  • Authors:
  • John M. Emmert;Dinesh Bhatia

  • Affiliations:
  • Design Automation Laboratory, ECECS Department, P. O. Box 210030, University of Cincinnati, Cincinnati, OH;Design Automation Laboratory, ECECS Department, P. O. Box 210030, University of Cincinnati, Cincinnati, OH

  • Venue:
  • FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
  • Year:
  • 1999

Quantified Score

Hi-index 0.01

Visualization

Abstract