A Network Flow Approach to the Reconfiguration of VLSI Arrays
IEEE Transactions on Computers
Incremental circuit simulation and timing analysis techniques
Incremental circuit simulation and timing analysis techniques
Compression-relaxation: a new approach to performance driven placement for regular architectures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Applications of slack neighborhood graphs to timing driven optimization problems in FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
DAC '97 Proceedings of the 34th annual Design Automation Conference
A methodology for fast FPGA floorplanning
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A Fault Tolerant Technique for FPGAs
Journal of Electronic Testing: Theory and Applications
On Using Tabu Search for Design Automation of VLSI Systems
Journal of Heuristics
Transformation from ad hoc EDA to algorithmic EDA
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Abstract: In a typical design flow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design specification either as a result of design debugging or as a result of changes in engineering requirements. These modifications are usually local and are referred to as engineering changes. In this paper we study the problem of timing driven placement re-engineering: the problem of altering the placement of a circuit to incorporate engineering changes without degrading the timing performance of the circuit. We focus on the re-engineering problem for regular architectures such as FPGAs and gate arrays. Our algorithms exploit the locality of the re-engineering design changes and use the current placement to generate the new placement for the altered circuit. Our experiments on the Xilinx 3000 FPGA architecture demonstrate the effectiveness of our algorithm in handling engineering changes efficiently.