Tight bounds for minimax grid matching, with applications to the average case analysis of algorithms
STOC '86 Proceedings of the eighteenth annual ACM symposium on Theory of computing
Field-programmable gate arrays
Field-programmable gate arrays
Re-engineering of timing constrained placements for regular architectures
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
REMOD: a new methodology for designing fault-tolerant arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Laser correcting defects to create transparent routing for large area FPGA's
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Graph Algorithms
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Using ILA Testing for BIST in FPGAs
Proceedings of the IEEE International Test Conference on Test and Design Validity
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Progress in autonomous fault recovery of field programmable gate arrays
ACM Computing Surveys (CSUR)
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In this paper we present a fault tolerant (FT) technique for field programmable gate arrays (FPGAs) that is based on incrementally reconfiguring circuits and applications that have been previously placed and routed. Our technique targets both logic faults and interconnect faults, and our algorithms can be applied to either static or run-time reconfigurable FPGAs. The algorithm for reconfiguring designs in the presence of logic faults uses a matching technique. The matching technique requires no preplaced, spare logic resources and is capable of handling groups of faults. Experimental results indicate there is little or no impact on circuit performance for low numbers of reconfigured logic blocks. For interconnect faults, we present a rip-up and reroute strategy. Our strategy is based on reading back the FPGA configuration memory, so no netlist is required for rerouting around faulty resources. Experimental results indicate high incremental routability for low numbers of interconnect faults. We also lay the foundation for applying our approach to yield enhancement.