Field-programmable gate arrays
Field-programmable gate arrays
Wafer-Scale Integration Using Restructurable VLSI
Computer - Special issue on wafer-scale integration
AnyBoard: An FPGA-Based, Reconfigurable System
IEEE Design & Test
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
The Teramac Custom Computer: Extending the Limits with Defect Tolerance
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Architectural and physical design challenges for one-million gate FPGAs and beyond
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
A Fault Tolerant Technique for FPGAs
Journal of Electronic Testing: Theory and Applications
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Creating large area FPGA's is limited by the presence of defective sections. The techniques developed in wafer scale work solve this problem by using defect avoidance routing around flawed blocks to build complete working systems. FPGA's have the main features required for successful defect avoidance systems: a repeatable cell, built in need for switchable flexible routing and high flexibility with potentially large number of applications. Laser formed connections and cuts have proved to be effective in bypassing fabrication time defects and creating defect free working systems up to wafer scale in area. Power shorts and clock distribution errors can effectively be eliminated using these laser links. In addition it is important to minimize signal delays so the bypassing of the defective cells is nearly invisible. Experiments on a small test FPGA shows defect avoidance routing using laser link structures generates delays which are about half those obtained by the active switches required for the FPGA's operation. Thus laser defect avoidance after fabrication removes the errors creating a large area FPGA whose defective cell distribution is nearly unseen by the user.