DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Amap: A technology mapper for selector-based field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Iterative wirability and performance improvement for FPGAs
DAC '93 Proceedings of the 30th international Design Automation Conference
IBM Journal of Research and Development
Laser correcting defects to create transparent routing for large area FPGA's
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
Using Laser Defect Avoidance to Build Large-Area FPGAs
IEEE Design & Test
Reconfiguring One-Time Programmable FPGAs
IEEE Micro
Performance Penalty for Fault Tolerance in Roving STARs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Fault Scanner for Reconfigurable Logic
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
BIST-Based Diagnostics of FPGA Logic Blocks
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
| Hi-index | 14.98 |
The field programmable gate array (FPGA) routing resources are fixed and their usage is constrained by the location of programmable interconnects (PIs) such as antifuses. The routing or the interconnect delays are determined by the length of segments assigned to the nets of various lengths and the number of PIs programmed for routing of each net. Due to the use of PIs certain unconventional faults may appear. In this paper we model the PI faults and address the design and routability of the FPGA channel architecture to achieve 100% routing with minimum performance penalty in the presence of PI faults. A channel routing algorithm has also been developed which routes nets in the presence of PI faults. Experiments were performed by randomly injecting faults of different types into the routing channel and then using the routing algorithm to determine the routability of the synthesized architecture. Results on a set of industrial designs and MCNC benchmark examples show the feasibility of achieving routability with minimum performance penalty when a large number of faults are present in the channel.