Logic synthesis for programmable gate arrays

Authors:
Rajeev Murgai;Yoshihito Nishizaki;Narendra Shenoy;Robert K. Brayton;Alberto Sangiovanni-Vincentelli
Affiliations:
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Kawasaki Steel Corporation, Tokyo, Japan and Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract

The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architectures: table-look-up and multiplexor-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources.