Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Technology mapping for a two-output RAM-based field programmable gate array
EURO-DAC '91 Proceedings of the conference on European design automation
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Compatible class encoding in hyper-function decomposition for FPGA synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe
Three parameters to find functional decompositions
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Finding an optimal functional decomposition for LUT-based FPGA synthesis
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimum Functional Decomposition for LUT-Based FPGA Synthesis
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
An Implicit Algorithm for Support Minimization during Functional Decomposition
EDTC '96 Proceedings of the 1996 European conference on Design and Test
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Effective and efficient FPGA synthesis through general functional decomposition
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Journal of Systems Architecture: the EUROMICRO Journal
An efficient algorithm for finding the minimal-area FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Information-driven circuit synthesis with the pre-characterized gate libraries
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
A relational approach to functional decomposition of logic circuits
ACM Transactions on Database Systems (TODS)
Computing support-minimal subfunctions during functional decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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