DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
FPGA design principles (a tutorial)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A CAD system for the design of field programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A heuristic method for FPGA technology mapping based on the edge visibility
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Area and delay mapping for table-look-up based field programmable gate arrays
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Maximal reduction of lookup-table based FPGAs
EURO-DAC '92 Proceedings of the conference on European design automation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Performance-driven simultaneous place and route for row-based FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Simultaneous depth and area minimization in LUT-based FPGA mapping
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance-driven simultaneous place and route for island-style FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Technology mapping of sequential circuits for LUT-based FPGAs for performance
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
General modeling and technology-mapping technique for LUT-based FPGAs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Cube-packing and two-level minimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Technology mapping for FPGAs with embedded memory blocks
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Optimal clock period FPGA technology mapping for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A tutorial on logic synthesis for lookup-table based FPGAs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Rectification method for lookup-table type FPGA's
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Simultaneous logic decomposition with technology mapping in FPGA designs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
General technology mapping for field-programmable gate arrays based on lookup tables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
A Fast Partitioning Method for PLA-Based FPGAs
IEEE Design & Test
On Routability for FPGAs under Faulty Conditions
IEEE Transactions on Computers
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Technology Mapper for Xilinx FPGAs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Technology mapping for a two-output RAM-based field programmable gate array
EURO-DAC '91 Proceedings of the conference on European design automation
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
An efficient algorithm for finding the minimal-area FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System Synthesis for Networks of Programmable Blocks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
FPGA technology mapping: a study of optimality
Proceedings of the 42nd annual Design Automation Conference
Efficient LUT-based FPGA technology mapping for power minimization
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Global delay optimization using structural choices
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
UbiComp'06 Proceedings of the 8th international conference on Ubiquitous Computing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Field Programmable Gate Arrays are new devices that combine the versatility of a Gate Array with the user-programmability of a PAL. This paper describes an algorithm for technology mapping of combinational logic into Field Programmable Gate Arrays that use lookup table memories to realize combinational functions. It is difficult to map into lookup tables using previous techniques because a single lookup table can perform a large number of logic functions, and prior approaches require each function to be instantiated separately in a library. The new algorithm, implemented in a program called Chortle uses the fact that a K-input lookup table can implement any Boolean function of K-inputs, and so does not require a library-based approach. Chortle takes advantage of this complete functionality to evaluate all possible decompositions of the input Boolean network nodes. It can determine the optimal (in area) mapping for fanout-free trees of combinational logic. In comparisons with the MIS II technology mapper, on MCNC-89 Logic Synthesis benchmarks Chortle achieves superior results in significantly less time. 1