Performance-driven simultaneous place and route for island-style FPGAs

Authors:
Sudip K. Nag;Rob A. Rutenbar
Affiliations:
Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA;Dept. of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

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Abstract

Abstract: Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty of accurately predicting wirability and delay during placement. A new performance-driven simultaneous placement/routing technique has been developed for island-style FPGA designs. On a set of industrial designs for Xilinx 4000-series FPGAs, our scheme produces 100% routed designs with 8%-15% improvement in delay when compared to the Xilinx XACT5.0 place and route system.