Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A new global routing algorithm for FPGAs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Orthogonal greedy coupling: a new optimization approach to 2-D FPGA routing
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-oriented placement and routing for field-programmable gate arrays
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Performance-driven simultaneous place and route for island-style FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1997 international symposium on Physical design
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven simultaneous placement and routing for FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TRACER-fpga: a router for RAM-based FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
HARP: hard-wired routing pattern FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Architecture-aware FPGA placement using metric embedding
Proceedings of the 43rd annual Design Automation Conference
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Criticality history guided FPGA placement algorithm for timing optimization
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, congestion, etc) based on geometric distance and/or channel density is no longer accurate for FPGAs. Researchers have shown that the number of segments, instead of geometric (Manhattan) distance, traveled by a net is the most crucial factor in controlling the routing delay and cost in an FPGA. Further, the congestion information of a routing channel shall be measured by the available segments of specific lengths, instead of the density in a channel alone. In this paper, we propose an architecture-driven metric for simultaneous FPGA placement and global routing. The new metric considers the available segments and their lengths to optimize the wiring cost for placement and global routing. Experiments by employing a cluster growth placement and maze routing to demonstrate the new metric show respective average reductions of 8%, 20%, and 19% in the number of tracks used (area), maximum net delay, and average net delay based on the Lucent Technologies ORCA2C-like and the Xilinx XC4000EX-like architectures, compared with the traditional metric of geometric distance and channel density.