Universal switch modules for FPGA design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Universal switch-module design for symmetric-array-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
An architecture-driven metric for simultaneous placement and global routing for FPGAs
Proceedings of the 37th Annual Design Automation Conference
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An accurate evaluation of routing density for symmetrical FPGAs
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
A router for symmetrical FPGAs based on exact routing density evaluation
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
IEEE Transactions on Computers
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We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net. Initially, nets are connected independently of one another. Conflicts among nets over the usage of interconnect resources are resolved iteratively by a rip-up and rerouter, which is guided by a simulated evolution-based optimization technique. The proposed approach has been implemented in a program called TRACER-fpga. As compared with CGE and SEGA, TRACER-fpga in general requires fewer routing tracks at the expense of longer wiring delay. It is suitable for low-speed applications such as hardware emulation