Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
A class of min-cut placement algorithms
25 years of DAC Papers on Twenty-five years of electronic design automation
Cost-sensitive analysis of communication protocols
PODC '90 Proceedings of the ninth annual ACM symposium on Principles of distributed computing
Minimum diameter spanning trees and related problems
SIAM Journal on Computing
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Plane parallel a maze router and its application to FPGAs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A new global routing algorithm for FPGAs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
A performance and routablity driven router for FPGAs considering path delays
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Performance-oriented placement and routing for field-programmable gate arrays
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Proceedings of the 1997 international symposium on Physical design
Balancing minimum spanning and shortest path trees
SODA '93 Proceedings of the fourth annual ACM-SIAM Symposium on Discrete algorithms
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Routing architectures and algorithms for field-programmable gate arrays
Routing architectures and algorithms for field-programmable gate arrays
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TRACER-fpga: a router for RAM-based FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An architecture-driven metric for simultaneous placement and global routing for FPGAs
Proceedings of the 37th Annual Design Automation Conference
Runtime and quality tradeoffs in FPGA placement and routing
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Graph matching-based algorithms for array-based FPGA segmentation design and routing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A novel approach to the placement and routing problems for field programmable gate arrays
Applied Soft Computing
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
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In this paper we present a timing-driven router for symmetrical array-based FPGAs. The routing resources in the FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a net is the most critical factor in controlling routing delay in an FPGA. Thus, the traditional measure of routing delay on the basis of geometric distance of a signal is not accurate. To consider wirelength and delay simultaneously, we study a model of timing-driven routing rees, arising from the special properties of FPGA routing architectures. Based on the solutions to the routing-tree problem, we present a routing algorithm that is able to utilize various routing segments with global considerations to meet timing constraints. Experimental results show that our approach is very effective in reducing timing violations.