A CAD system for the design of field programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Iterative and adaptive slack allocation for performance-driven layout and FPGA routing
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance of interconnection rip-up and reroute strategies
DAC '81 Proceedings of the 18th Design Automation Conference
An iterative-improvement penalty-function-driven wire routing system
IBM Journal of Research and Development
Performance-driven simultaneous place and route for island-style FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Emerald: an architecture-driven tool compiler for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Proceedings of the 1997 international symposium on Physical design
New parallelization and convergence results for NC: a negotiation-based FPGA router
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
DUNE: a multi-layer gridless routing system with wire planning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
An architecture-driven metric for simultaneous placement and global routing for FPGAs
Proceedings of the 37th Annual Design Automation Conference
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
LRoute: a delay minimal router for hierarchical CPLDs
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Runtime and quality tradeoffs in FPGA placement and routing
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The case for registered routing switches in field programmable gate arrays
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Proceedings of the 2001 international symposium on Physical design
A comparative study of two Boolean formulations of FPGA detailed routing constraints
Proceedings of the 2001 international symposium on Physical design
Integrated retiming and placement for field programmable gate arrays
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Timing-driven routing for FPGAs based on Lagrangian relaxation
Proceedings of the 2002 international symposium on Physical design
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
On metrics for comparing routability estimation methods for FPGAs
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Performance-driven placement for dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wire type assignment for FPGA routing
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
PipeRoute: a pipelining-aware router for FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Stochastic, spatial routing for hypergraphs, trees, and meshes
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Placement-driven technology mapping for LUT-based FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design of FPGA interconnect for multilevel metalization
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Minimizing FPGA Interconnect Delays
IEEE Design & Test
Tightly Integrated Placement and Routing for FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Placing, Routing, and Editing Virtual FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
TDR: A Distributed-Memory Parallel Routing Algorithm for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Incremental placement for layout driven optimizations on FPGAs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On Routing Demand and Congestion Estimation for FPGAs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Exploration of pipelined FPGA interconnect structures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints
IEEE Transactions on Computers
Design automation for mask programmable fabrics
Proceedings of the 41st annual Design Automation Conference
A Min-Cost Flow Based Detailed Router for FPGAs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On metrics for comparing interconnect estimation methods for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Proceedings of the 32nd annual international symposium on Computer Architecture
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Physical resource binding for a Coarse-Grain reconfigurable array using evolutionary algorithms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and evaluation of a hybrid interconnect structure for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improving performance and robustness of domain-specific CPLDs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Armada: timing-driven pipeline-aware routing for FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Droplet routing in the synthesis of digital microfluidic biochips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Proceedings of the 2007 international symposium on Physical design
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BioRoute: a network-flow based routing algorithm for digital microfluidic biochips
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 2008 international symposium on Physical design
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
A new global router for modern designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient tree topology for FPGA interconnect network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhancing timing-driven FPGA placement for pipelined netlists
Proceedings of the 45th annual Design Automation Conference
High-level modelling and exploration of coarse-grained re-configurable architectures
Proceedings of the conference on Design, automation and test in Europe
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
SPR: an architecture-adaptive CGRA mapping tool
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute3.0: a fast and high quality global router based on virtual capacity
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-layer global routing considering via and wire capacities
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A routing approach to reduce glitches in low power FPGAs
Proceedings of the 2009 international symposium on Physical design
Diffusion-driven congestion reduction for substrate topological routing
Proceedings of the 2009 international symposium on Physical design
A design flow for architecture exploration and implementation of partially reconfigurable processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Configuration Sharing to Reduce Reconfiguration Overhead Using Static Partial Reconfiguration
IEICE - Transactions on Information and Systems
Towards a framework for designing applications onto hybrid nano/CMOS fabrics
Microelectronics Journal
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Slotless module-based reconfiguration of embedded FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
Automatic bus planner for dense PCBs
Proceedings of the 46th Annual Design Automation Conference
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
BSG-route: a length-constrained routing scheme for general planar topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA interconnect topologies exploration
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
A multilevel congestion-based global router
VLSI Design
Completing high-quality global routes
Proceedings of the 19th international symposium on Physical design
A routing approach to reduce glitches in low power FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-threaded collision-aware global routing with bounded-length maze routing
Proceedings of the 47th Design Automation Conference
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NTHU-route 2.0: a robust global router for modern designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Torc: towards an open-source tool flow
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Exploration of FPGA interconnect for the design of unconventional antennas
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Routing with graphene nanoribbons
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Negotiation-based layer assignment for via count and via overflow minimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Extended global routing with RLC crosstalk constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Comparison between heterogeneous mesh-based and tree-based application specific FPGA
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Exploration of heterogeneous FPGA architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Mesh routing topologies for multi-FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-Specific FPGA using heterogeneous logic blocks
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An FPGA-based heterogeneous coarse-grained dynamically reconfigurable architecture
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
Regular 2D NASIC-based architecture and design space exploration
NANOARCH '11 Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reliability-Driven Power/Ground Routing for Analog ICs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application specific FPGA using heterogeneous logic blocks
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
TROUTE: a reconfigurability-aware FPGA router
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Exploring high throughput computing paradigm for global routing
Proceedings of the International Conference on Computer-Aided Design
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
A SAT-based routing algorithm for cross-referencing biochips
Proceedings of the System Level Interconnect Prediction Workshop
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MDE-based FPGA physical design: fast model-driven prototyping with Smalltalk
Proceedings of the International Workshop on Smalltalk Technologies
Networked architecture for hybrid electrical energy storage systems
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
A connection router for the dynamic reconfiguration of FPGAs
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
A low-overhead interconnect architecture for virtual reconfigurable fabrics
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
BPR: fast FPGA placement and routing using macroblocks
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Microprocessors & Microsystems
Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
A novel multithread routing method for FPGAs (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Delay-driven layer assignment in global routing under multi-tier interconnect structure
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Iterative routing algorithm of Inter-FPGA signals for Multi-FPGA prototyping platform
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
High-level modeling and synthesis for embedded FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance
Proceedings of the 50th Annual Design Automation Conference
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography
Proceedings of the 50th Annual Design Automation Conference
Routability optimization for crossbar-switch structured ASIC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
JITPR: A framework for supporting fast application's implementation onto FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Towards development of an analytical model relating FPGA architecture parameters to routability
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)
A routing algorithm for graphene nanoribbon circuit
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Towards interconnect-adaptive packing for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Optimizing effective interconnect capacitance for FPGA power reduction
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures
ACM Transactions on Architecture and Code Optimization (TACO)
A just-in-time customizable processor
Proceedings of the International Conference on Computer-Aided Design
A low-cost fault tolerant solution targeting commercial FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
A novel 3-D FPGA architecture targeting communication intensive applications
Journal of Systems Architecture: the EUROMICRO Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2014 on International symposium on physical design
Impact of dual placement and routing on WDDL netlist security in FPGA
International Journal of Reconfigurable Computing
Frequency optimization objective during system prototyping on multi-FPGA platform
International Journal of Reconfigurable Computing
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Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.