High-level modeling and synthesis for embedded FPGAs

Authors:
Xiaolin Chen;Shuai Li;Jochen Schleifer;Thomas Coenen;Anupam Chattopadhyay;Gerd Ascheid;Tobias G. Noll
Affiliations:
RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2013

Citing 8
Cited 1

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FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research

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The Chimaera reconfigurable functional unit

FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only)

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic

ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Design flow for embedded FPGAs based on a flexible architecture template

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FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP

FCCM '12 Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

Ingredients of adaptability: a survey of reconfigurable processors

VLSI Design

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Abstract

The fast evolving applications in modern digital signal processing have an increasing demand for components which have high computational power and energy efficiency without compromising the flexibility. Embedded FPGA, which is the customized FPGA with heterogeneous fine-grained application specific operations and routing resources, has shown significantly improved efficiency in terms of throughput, power dissipation and chip area for the target application domain. On the other hand, the complexity of such architecture makes it difficult to perform an efficient architecture exploration and application synthesis without tool support. In this work, we propose a framework for the design of embedded FPGA (eFPGA) architectures, which is extended from an existing framework for Coarse-Grained Reconfigurable Architectures (CGRAs). The framework is composed of a high-level modeling formalism for eFPGAs to explore the mapping space, and a retargetable application synthesis flow. To enable fast design space exploration, a force-directed placement algorithm is proposed. Finally, we demonstrate the efficacy of this framework with demanding application kernels.