Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic

Authors:
T. von Sydow;B. Neumann;H. Blume;T. G. Noll
Affiliations:
RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany;RWTH Aachen University, Germany
Venue:
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Year:
2006

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Abstract

Embedding FPGAs (eFPGAs) in modern SoCs provides a high amount of flexibility while highthroughput digital signal processing algorithms can be realised efficiently. An analysis of eFPGA architectures and corresponding structural elements is presented to determine the optimisation potential for eFPGAs tailored to an arithmetic oriented application domain. The applied design flow incorporating an automated layout generation approach and the utilised simulation environment is discussed. An eFPGA macro designed and realised for arithmetic oriented applications is quantitatively compared to an actual commercial FPGA in terms of area, power consumption and delay time. It can be shown that this optimised eFPGA macro outperforms a state of the art commercial device for a couple of arithmetic operators which are commonly applied in arithmetic datapaths.