PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Interconnect Technology and Design for Gigascale Integration
Interconnect Technology and Design for Gigascale Integration
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
A polynomial time approximation scheme for timing constrained minimum cost layer assignment
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-layer global routing considering via and wire capacities
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Robust layer assignment for via optimization in multi-layer global routing
Proceedings of the 2009 international symposium on Physical design
Proceedings of the 2009 International Conference on Computer-Aided Design
Negotiation-based layer assignment for via count and via overflow minimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
Proceedings of the International Conference on Computer-Aided Design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
Optimizing the antenna area and separators in layer assignment of multi-layer global routing
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
An efficient approach to multilayer layer assignment with an application to via minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of the maximum delay of global interconnects during layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Performance Routing at the Nanometer Scale
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
A multilayer routing system usually adopts multiple interconnect configuration with different wire sizes and thicknesses. Since thicker layers of metal lead to fatter wires with smaller resistance, the layer assignment of nets has a large impact on the interconnect delay. However, such layer dependent characteristics have been ignored by most of the state-of-the-art academic layer assignment methods. To remedy this deficiency, this work studies a more effective layer assignment problem under such multi-tier interconnect structure, which arises during 3D global routing and focuses on minimizing both delays and via count. This work presents a two-stage algorithm to solve the problem, which first minimizes the total delay and via count simultaneously by dynamic programming and negotiation technique, and then further minimizes the maximum delay carefully while not increasing the via count. The experimental results on ICCAD09 benchmarks show that the proposed algorithm can significantly reduce the total delay and maximum delay while still keeping roughly the same via count, compared with the state-of-the-art via count minimization layer assignment method NVM.