The Via Minimization Problem is NP-Complete
IEEE Transactions on Computers
Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
MaizeRouter: engineering an effective global router
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Robust layer assignment for via optimization in multi-layer global routing
Proceedings of the 2009 international symposium on Physical design
Multi-threaded collision-aware global routing with bounded-length maze routing
Proceedings of the 47th Design Automation Conference
Negotiation-based layer assignment for via count and via overflow minimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Antenna avoidance in layer assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-Performance Routing at the Nanometer Scale
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay-driven layer assignment in global routing under multi-tier interconnect structure
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Traditional solutions to antenna effect, such as jumper insertion and diode insertion peformed at post-route stage may produce extra vias and degrade circuit performance. The work in [1] suggests combining layer assignment, jumper insertion and diode insertion together to achieve a better design quality with less additional cost. Based on our observations on global and local antenna violations, this work proposes a dynamic-programming based single-net layer assignment called NALAR, which first enumerates all antenna-violation-safe layer assignment solutions of a net, and then extracts the minimum-cost one for the net. NALAR can minimize via count and separators as well. In addition, an antenna avoidance layer assignment algorithm (ANLA) adopting NALAR as its kernel not only avoids global antenna violations, but also eliminates local antenna violations. Experimental results reveal that, in 11 benchmarks, ANLA can yield 5 violation-free assignments while the algorithms of other works yield no violation-free assignment. As for the total number of antenna violations in all benchmarks, this work and the works in [2], [3] and [4] yield 21, 43506, 41261 and 29671 antenna violations, respectively. However, ANLA performs about 7 times slower than other antenna-aware layer assignment [4].