PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Improved global routing through congestion estimation
Proceedings of the 40th annual Design Automation Conference
Length-Matching Routing for High-Speed Printed Circuit Boards
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Optimizing yield in global routing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Timing-driven routing for FPGAs based on Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
A new global router for modern designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute3.0: a fast and high quality global router based on virtual capacity
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-layer global routing considering via and wire capacities
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Robust layer assignment for via optimization in multi-layer global routing
Proceedings of the 2009 international symposium on Physical design
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
Automatic bus planner for dense PCBs
Proceedings of the 46th Annual Design Automation Conference
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-threaded collision-aware global routing with bounded-length maze routing
Proceedings of the 47th Design Automation Conference
Routing with graphene nanoribbons
Proceedings of the 16th Asia and South Pacific Design Automation Conference
High-quality global routing for multiple dynamic supply voltage designs
Proceedings of the International Conference on Computer-Aided Design
Exploring high throughput computing paradigm for global routing
Proceedings of the International Conference on Computer-Aided Design
An auction based pre-processing technique to determine detour in global routing
Proceedings of the International Conference on Computer-Aided Design
GLADE: a modern global router considering layer directives
Proceedings of the International Conference on Computer-Aided Design
Optimizing the antenna area and separators in layer assignment of multi-layer global routing
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
A routing algorithm for graphene nanoribbon circuit
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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Global routing is an important step in the physical design process. In this paper, we propose a new global routing algorithm Archer, which resolves some of the most common problems with the state-of-the-art global routers. It is known that concurrent global routing algorithms are typically too expensive to be applied on today's large designs, which may contain up to a million nets. On the other hand, iterative rip-up and reroute (RNR) based algorithms are susceptible to getting stuck in local optimal solutions. In this paper, we propose an RNR-based global routing algorithm that guides the routing iterations out of local optima through effective usage of congestion histories. We also focus on the problem of how to enable a smooth trade-off between seemingly conflicting objectives of overflow and wirelength minimization. Furthermore, we propose a Lagrangian relaxation based bounded-length min-cost topology improvement algorithm that enables Steiner trees to change dynamically for the purpose of congestion optimization. Our experiments show that Archer obtains congestion-free solutions for all circuits in the standard ISPD98 benchmarks, which is the best result published so far. Furthermore, it produces better results than the best results reported in the ISPD-07 Global Routing Contest in terms of routability. Compared to FastRoute [18, 19], which is the state-of-the-art RNR-based global routing algorithm, Archer improves routability by 30%, and reduces the wirelengths by 32% on the average on ISPD07 benchmarks.