Introduction to algorithms
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Directional bias and non-uniformity in FPGA global routing architectures
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
New Lagrangian relaxation based algorithm for resource scheduling with homogeneous subproblems
Journal of Optimization Theory and Applications
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Equidistance routing in high-speed VLSI layout design
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Simultaneous escape routing and layer assignment for dense PCBs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A provably good algorithm for high performance bus routing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Two-layer bus routing for high-speed printed circuit boards
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An escape routing framework for dense boards with high-speed design constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Untangling twisted nets for bus routing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Archer: a history-based global routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Optimal simultaneous pin assignment and escape routing for dense PCBs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
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As the clock frequencies used in industrial applications increase,the timing requirements imposed on routing problems becometighter. So, it becomes important to route the nets within tight minimumand maximum length bounds. Although the problem of routingnets to satisfy maximum length constraints is a well-studiedproblem, there exists no sophisticated algorithm in the literaturethat ensures that minimum length constraints are also satisfied. Inthis paper, we propose a novel algorithm that effectively incorporatesthe min-max length constraints into the routing problem. Ourapproach is to use a Lagrangian relaxation framework to allocateextra routing resources around nets simultaneously during routingthem. We also propose a graph model that ensures that all theallocated routing resources can be used effectively for extendinglengths. Our routing algorithm automatically prioritizes resourceallocation for shorter nets, and length minimization for longer netsso that all nets can satisfy their min-max length constraints. Ourexperiments demonstrate that this algorithm is effective even in thecases where length constraints are tight, and the layout is dense.