Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal river routing with crosstalk constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
General river routing algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
On routing two-point nets across a channel
DAC '82 Proceedings of the 19th Design Automation Conference
Length-Matching Routing for High-Speed Printed Circuit Boards
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing-driven routing for FPGAs based on Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An escape routing framework for dense boards with high-speed design constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Untangling twisted nets for bus routing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Algorithms and theory of computation handbook
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
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As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools can not successfully handle these constraints any more. We focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing; and use those resources for length extension afterwards. We first propose a provably optimal algorithm for routing nets with min-area max-length constraints. Then, we extend this algorithm to the case where minimum constraints are given as exact length bounds. We also prove that this algorithm is optimal within a constant factor. Both algorithms proposed are also shown to be scalable for large circuits, since the respective time complexities are O(A) and O(A log A), where A is the area of the intermediate region between chips.