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RDL pre-assignment routing for flip-chip designs
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IO connection assignment and RDL routing for flip-chip designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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A general and practical river routing algorithm is described. It is assumed that there is one layer for routing and terminals are on the boundaries of an arbitrarily shaped rectilinear routing region. All nets are two-terminal nets with pre-assigned (may be different) widths and no crossover between nets is allowed. The minimum separation between the edges of two adjacent wires is input as the design rule. This algorithm assumes no grid on the plane and will always generate a solution if a solution exists. The number of corners is reduced by flipping of corners. An analysis to determine the minimum space required for a strait-type river routing problem is included. Let B be the number of boundary segments and T be the total number of terminals. The time complexity is of O(T(B+T)2) and the storage required is O((B+T)2). This algorithm is implemented as part of the design station under development at the University of California, Berkeley.