A fast algorithm to test planar topological routability

Authors:
A. Lim;S. Sahni;V. Thanvantri
Affiliations:
-;-;-
Venue:
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Year:
1995

Citing 6
Cited 1

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Abstract

We develop a simple linear time algorithm to determine if a collection of two pin nets can be routed, topologically, in a plane (i.e. single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng (1983).