Pin assignment and routing on a single-layer Pin Grid Array
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Introduction to Algorithms
A timing-constrained algorithm for simultaneous global routing of multiple nets
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
General river routing algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
An Even Wiring Approach to the Ball Grid Array Package Routing
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
NEWS: a net-even-wiring system for the routing on a multilayer PGA package
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Min-cost flow-based algorithm for simultaneous pin assignment and routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IO connection assignment and RDL routing for flip-chip designs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On using SAT to ordered escape problems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Octilinear redistributive routing in bump arrays
Proceedings of the 19th ACM Great Lakes symposium on VLSI
RDL pre-assignment routing for flip-chip designs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
B-escape: a simultaneous escape routing algorithm based on boundary routing
Proceedings of the 19th international symposium on Physical design
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered escape routing via routability-driven pin assignment
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IO connection assignment and RDL routing for flip-chip designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
On effective flip-chip routing via pseudo single redistribution layer
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The flip-chip package gives the highest chip density of any packaging method to support the pad-limited Application-Specific Integrated Circuit (ASIC) designs. In this paper, we propose the first router for the flip-chip package in the literature. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads, and then create the global routing path for each net. The detailed routing consists of three stages, cross point assignment, net ordering determination, and track assignment, to complete the routing. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, compared with a heuristic algorithm currently used in industry.