Introduction to algorithms
General river routing algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
IO connection assignment and RDL routing for flip-chip designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Based on the concept of net renumbering and recovery to simplify the complexity of the global and detailed routing, an efficient RDL pre-assignment routing algorithm is proposed to maximize the number of routed nets with the minimization of total wirelength under the crossing and capacitance constraints for a flip-chip design. Compared with the combination of the single-layer BGA global router[6] and our detailed routing, our RDL pre-assignment router reduces the global wirelength by 12.8% after global routing and improve the routability by 14.7% after detailed routing on the average for some tested circuits in reasonable CPU time.