Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Wirelength reduction by using diagonal wire
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Ordered escape routing based on Boolean satisfiability
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Topological routing to maximize routability for package substrate
Proceedings of the 45th annual Design Automation Conference
Routing for chip-package-board co-design considering differential pairs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IO connection assignment and RDL routing for flip-chip designs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On using SAT to ordered escape problems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
RDL pre-assignment routing for flip-chip designs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
Proceedings of the 46th Annual Design Automation Conference
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient pre-assignment routing algorithm for flip-chip designs
Proceedings of the 2009 International Conference on Computer-Aided Design
B-escape: a simultaneous escape routing algorithm based on boundary routing
Proceedings of the 19th international symposium on Physical design
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Ordered escape routing via routability-driven pin assignment
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IO connection assignment and RDL routing for flip-chip designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
On effective flip-chip routing via pseudo single redistribution layer
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literature for the pre-assignment flip-chip routing problem with a pre-defined netlist among pads and wire-width and signal-skew considerations. Our algorithm is based on integer linear programming (ILP) and guarantees to find an optimal solution for the addressed problem. It adopts a two-stage technique of global routing followed by detailed routing. In global routing, it first uses two reduction techniques to prune redundant solutions and create a global-routing path for each net. Without loss of the solution optimality, our reduction techniques can further prune the ILP variables (constraints) by 85.5% (98.0%) on average over a recent reduction technique. The detailed routing applies X-based grid-less routing to complete the routing. Experimental results based on five real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all signal-skew constraints, under reasonable CPU times, while recent related work results in much inferior solution quality.