Topological routing to maximize routability for package substrate

Authors:
Shenghua Liu;Guoqiang Chen;Tom Tong Jing;Lei He;Tianpei Zhang;Robi Dutta;Xian-Long Hong
Affiliations:
Tsinghua University, Beijing, China;Magma Design Automation, Inc., San Jose, CA;University of California at Los Angeles, Los Angeles, CA;University of California at Los Angeles, Los Angeles, CA;University of Minnesota, Minneapolis, MN;Magma Design Automation, Inc., San Jose, CA;Tsinghua University, Beijing, China
Venue:
Proceedings of the 45th annual Design Automation Conference
Year:
2008

Citing 6
Cited 3

Pin assignment and routing on a single-layer Pin Grid Array

ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Interchangeable pin routing with application to package layout

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SURF: Rubber-Band Routing System for Multichip Modules

IEEE Design & Test
A global routing method for 2-layer ball grid array packages

Proceedings of the 2005 international symposium on Physical design
An integer linear programming based routing algorithm for flip-chip design

Proceedings of the 44th annual Design Automation Conference
NEWS: a net-even-wiring system for the routing on a multilayer PGA package

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Diffusion-driven congestion reduction for substrate topological routing

Proceedings of the 2009 international symposium on Physical design
Effective congestion reduction for IC package substrate routing

ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-in-Package: Electrical and Layout Perspectives

Foundations and Trends in Electronic Design Automation

Quantified Score

Hi-index	0.00

Visualization

Abstract

Compared with on-chip routers, the existing commercial tools for off-chip routing have a much lower routability and often result in a large number of unrouted nets for manual routing. In this paper, we develop an effective, yet efficient, substrate routing algorithm, applying dynamic pushing to alleviate the net ordering problem and reordering and rerouting for further wire length and congestion reduction. Compared with an industrial design tool that leaves 936 nets unrouted for nine industrial designs with a total of 6100 nets, our algorithm reduces the unrouted nets to 212, a 4.5-times net number reduction and practically more design time reduction.